A ferroelectric non-volatile memory cell consists of a select, or access, transistor and a storage capacitor whose dielectric is a ferroelectric material film. By applying an electric field of sufficient strength across the storage capacitor, the ferroelectric material is polarized in the direction of the electric field, and the acquired polarization is retained after the electric field is removed. If an electric field of sufficient strength and direction opposite to the polarization direction is subsequently applied, the ferroelectric material becomes and remains polarized in such an opposite direction even after the electric field is removed. The effect of the polarization is a non-zero charge per unit storage capacitor area that exists even when no voltage is applied across the capacitor and does not disappear in time. Information can thus be stored in the memory cell by associating the two opposite directions of polarization of the storage capacitor ferroelectric material with the two logic states “1” and “0”.
Due to the similarity of the ferroelectric non-volatile memory cell with the dynamic RAM (DRAM) memory cell, the former is also referred to as ferroelectric RAM or FeRAM.
Two families of FeRAMs are known in the art, which differ from each other by the number of memory cells employed to store a single data bit.
FeRAMs of a first family use a single memory cell as a bit storage unit, and are for this reason also referred to as “1T1C” (one transistor, one capacitor). Thanks to the simplicity of the bit storage unit, this kind of approach is suitable for achieving very large memory sizes, on the order of megabits.
A “1T1C” FeRAM cell read process involves a sharing of the charge of the memory cell storage capacitor with the parasitic capacitance of the respective bit line. A voltage thus develops on the bit line which, through the respective select transistor, is electrically connected to the storage capacitor. The bit line voltage can take one of two different values, depending on the polarization of the storage capacitor. A sense amplifier, typically a comparator fed with the bit line voltage and with a reference voltage, discriminates between the two possible voltage values and provides the stored data bit by comparing the bit line voltage to the reference voltage.
A problem with the “1T1C” approach are the difficulties inherent in the generation of the reference voltage to be supplied to the sense amplifier. The reference voltage typically must be sufficiently accurate for discriminating between the two voltage values which can develop on the bit line. In particular, the difficulties arise from the fact that the reference voltage must assure the possibility of discriminating between the two voltage values in any condition of temperature, supply voltage, process variations and storage capacitor degradation within the specified ratings. In order to comply with these requirements, complex circuitry must be provided for, which has a negative impact on the memory chip size. Another problem affecting the “1T1C” approach is that the read margin, i.e. the difference between the two possible voltage values that develop on the bit line, decreases as the bit line length increases, due to the increase in the bit line parasitic capacitance.
A second family of FeRAMs has bit storage units made up of two memory cells, and is for this reason referred to as “2T2C” (two transistors, two capacitors). Considering a generic bit storage unit, the two storage capacitors are at any time polarized in mutually opposite directions (i.e., they store opposite logic states), except during the read and write operations. In order to read the data bit stored in a bit storage unit, a same electric field is applied across both the capacitors; as a result, the polarization of one capacitor is simply confirmed, while that of the other capacitor is reversed. The change in polarization of the capacitor results in a charge on the bit line which, through the respective select transistor, is electrically connected to the storage capacitor. The sense amplifier is typically made up of two CMOS inverters connected in a latch configuration to both the bit lines; by choosing a convention for the connection of the sense amplifier inputs to the two bit lines, one pair of mutually opposite polarization states of the capacitors is interpreted as a logic “1”, while the other pair of mutually opposite polarization states is interpreted as a logic “0”.
This bit storage unit architecture does not suffer of the problems of the “1T1C” one, since no reference levels are needed for sensing the bit storage unit. For this reason, this architecture is also referred to as self-referenced. However, the “2T2C” architecture is not suitable for large size memories, because the array of bit storage units contains twice the number of memory cells as the “1T1C” one.